10aucti, dnc. 20 stern ave. springfield, new jersey 07081 u.s.a. telephone: (973) 376-2922 (212)227-6005 fax: (973) 376-8960 designer's? data sheet tmos e-fet ? power field effect transistor n-channel enhancement-mode silicon gate this high voltage mosfet uses an advanced termination scheme to provide enhanced voltage-blocking capability without degrading performance over time. in addition, this advanced tmos e-fet is designed to withstand high energy in the avalanche and commutation modes. the new energy efficient design also offers a drain-to-source diode with a fast recovery time. designed for high voltage, high speed switching applications in power supplies, converters and pwm motor controls, these devices are particularly well suited for bridge circuits where diode speed and commutating safe operating areas are critical and offer additional safety margin against unexpected voltage transients. ? robust high voltage termination ? avalanche energy specified ? source-to-drain diode recovery time comparable to a discrete fast recovery diode ? diode is characterized for use in bridge circuits ? 'dss and vos(on) specified at elevated temperature g o maximum ratings (tc = 25c unless otherwise noted) MTP4N80E if tmos tmos power fet 4.0 amperes 800 volts rds(on) = 3.0 o s to-220ab rating drain-source voltage drain-gate voltage (rgs = 1 -0 m2) gate-source voltage ? continuous ? non-repetitive (tp < 10 ms) drain current ? continuous ? continuous @ 100c ? single pulse (tp < 10 us) total power dissipation derate above 25c operating and storage temperature range single pulse drain-to-source avalanche energy ? starting tj = 25c (vdd = 100 vdc, vqs = 10 vdc, l|_ = s.o apk, l = 10 mh, rg = 25 1) thermal resistance ? junction to case ? junction to ambient maximum lead temperature for soldering purposes, 1/8" from case for 10 seconds symbol vdss vdgr vgs vgsm id id idm pd tj, ts,g eas r9jc r9ja tl value 800 800 20 40 4.0 2.9 12 125 1.0 -55 to 150 320 1.0 62.5 260 unit vdc vdc vdc vpk adc apk watts w/c c mj c/w c nj semi-conductors reserves the right to change test conditions, parameter limits and package dimensions without notice. information furnished by nj semi-conductors is believed to be both accurate and reliable at the time of going to press. however, nj semi-conductors assumes no responsibility for any errors or omissions discovered in its use. nj semi-conductors encourages customers to verity that datasheets are current before placing orders. quality semi-conductors
mtp4n8oe electrical characteristics (tj = 25c unless otherwise noted) characteristic symbol win typ max unit off characteristics drain-source breakdown voltage (vgs = o vdc, id = 250 uadc) temperature coefficient (positive) zero gate voltage drain current (vds = 800 vdc, vqs = vdc) (vds = 800 vdc, vgs = vdc, tj = 125c) gate-body leakage current (vgs = 20 vdc, vqs = 0) v(br)dss bss !gss 800 i ? 1.02 i ? ? 10 100 100 vdc mv/c hadc nadc on characteristics (1) gate threshold voltage (vds = vgs, id = 250 uadc) temperature coefficient (negative) static drain-source on-resistance (vgs = 10 vdc, id = 2.0 adc) drain-source on-voltage (vqs = 10 vdc) (id = 4.0 adc) (id = 2.0 adc, tj = 125c) forward transconductance (vds = 15 vdc, id = 2.0 adc) vgs(th) rds(on) vds(on) 9fs 2.0 ? i 2.0 3.0 7.0 1.95 8.24 4.3 4.0 3.0 12 10 ? vdc mv/c ohm vdc mhos dynamic characteristics input capacitance output capacitance reverse transfer capacitance (vds - 25 vdc, vgs = vdc, f= 1.0 mhz) cjss cqss crss ? ? ? 1320 187 72 2030 400 160 pf switching characteristics (2) turn-on delay time rise time turn-off delay time fall time gate charge (vdd = 400 vdc, id = 4.0 adc, \//->o - 1fi \/hr rg = 9.1 a.) (vds = 40 vdc, id = 4.0 adc, vgs = 10 vdc) td(on) tr td(off) tf qt qi q2 q3 ? ? ? _ _ ? ? ? 13 36 40 30 36 7.0 16.5 12 30 90 80 75 80 ? ? ? ns nc source-drain diode characteristics forward on-voltage (1) reverse recovery time (see figure 14) reverse recovery stored charge (is = 4.0 adc, vgs = 0 vdc) (is = 4.0 adc, vgs = vdc, tj = 125c) (is = 4.0 adc, vgs = vdc, dls/dt= 100 a/us) vsd trr ta tb qrr ? ? ? ? ? 0.812 0.7 557 100 457 2.33 1.5 _ ? ? ? vdc ns uc internal package inductance internal drain inductance (measured from contact screw on tab to center of die) (measured from the drain lead 0.25" from package to center of die) internal source inductance (measured from the source lead 0.25" from package to source bond pad) ld ls ? ? 3.5 4.5 7.5 ? ? nh nh (1) pulse test: pulse width < 300 us, duty cycle < 2%. (2) switching characteristics are independent of operating junction temperature.
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